List of Publications - Jonathan Rose

Patents

J. Rose and V. Betz, "Complementary Architectures for Field-Programmable Gate Arrays," U.S. Patent #5,537,341, filed February 10, 1995, issued July 16th, 1996.

Books

S. Brown, R. Francis, J. Rose, Z. Vranesic, Field-Programmable Gate Arrays, Kluwer Academic Publishers, May 1992.

Journal Papers

  1. V. Betz and J. Rose, "Effect of the Prefabricated Routing Track Distribution on FPGA Area-Efficiency," to appear in IEEE Transactions on VLSI. PostScript.
  2. P. Chow, S. O. Seo, J. Rose, K. Chung, I. Rahardja and G. Paez, "Architecture and Circuit-Level Design of an SRAM-Based Field-Programmable Gate Array," to appear in IEEE Transactions on VLSI. Postscript
  3. S. Brown and J. Rose, "FPGA and CPLD Architectures: A Tutorial," in IEEE Design and Test of Computers, Vol. 12, No. 2, Summer 1996, pp. 42-57.
  4. S. Brown, J. Rose, Z. Vranesic, "A Stochastic Model to Predict The Routability of Field-Programmable Gate Arrays," IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 12, No. 12, December 1993, pp. 1827-1838. Postscript
  5. J. Rose, A. El Gamal, A. Sangiovanni-Vincentelli, "Architecture of Field-Programmable Gate Arrays," in Proceedings of the IEEE, Vol. 81, No. 7, July 1993, pp. 1013-1029.
  6. A. Sangiovanni-Vincentelli, A. El Gamal, J. Rose, "Synthesis Methods for Field-Programmable Gate Arrays," in Proceedings of the IEEE, Vol. 81, No. 7, July 1993, pp. 1057-1083.
  7. S. Singh, J. Rose, P. Chow, D. Lewis, "The Effect of Logic Block Architecture on FPGA Performance," IEEE JSSC, Vol. 27 No. 3, March 1992, pp. 281-287.
  8. S. Brown, J.S. Rose, Z. Vranesic, " A Detailed Router for Field Programmable Gate Arrays," IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 11, No. 5, May 1992, pp. 620-628.
  9. J.S. Rose, S. Brown, " Flexibility of Interconnection Structures for Field-Programmable Gate Arrays ", IEEE JSSC Vol. 26 No. 3, March 1991, pp. 277-282.
  10. J.S. Rose, R.J. Francis, D. Lewis, and P. Chow, "Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency," IEEE JSSC, Vol. 25 No. 5, October 1990, pp. 1217-1225.
  11. J.S. Rose, "Parallel Global Routing for Standard Cells," IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 9, No. 10, October 1990, pp. 1085-1095.
  12. J.S. Rose, W. Klebsch, J. Wolf, "Temperature Measurement and Equilibrium Dynamics of Simulated Annealing Placements," IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 9, No. 3, March 1990, pp. 253-259.
  13. J.S. Rose, W.M. Snelgrove, Z.G. Vranesic, "Parallel Standard Cell Placement Algorithms with Quality Equivalent to Simulated Annealing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 7, Number 3, March 1988, pp. 387-396.
  14. J.S. Rose, Z.G. Vranesic, W.M. Loucks, "FERMTOR: A Tunable Multiprocessor Architecture," IEEE MICRO, Vol. 5, No. 4, August 1985, pp. 5-17.

Submitted Journal Papers

  1. S. Wilton, J. Rose, Z. Vranesic, "Stand-alone Field-Configurable Memory Architectures," sub. to IEEE Trans. on VLSI, January 1997.
  2. M. Hutton, J. Rose, J. Grossman, and D. Corneil, "Characterization and Parameterized Random Generation of Combinational Benchmark Circuits," sub. to IEEE Trans. on CAD, Feb 1997.
  3. S. Wilton, J. Rose, Z. Vranesic, "The Memory/Logic Interface in FPGAs with Large Embedded Memory Arrays," sub. to IEEE Trans. on VLSI, March 1997.

Refereed Papers in Conferences

  1. V. Betz and J. Rose, "Cluster-Based Logic Blocks for FPGAs: Area-Efficiency vs. Input Sharing and Size," in IEEE CICC 1997, Santa Clara, CA, pp. 551-554. Postscript
  2. J. Rose and D. Hill, "Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond," in FPGA `97, ACM Symp. on FPGAs, Feb 1997, pp. 129-132 (invited) Postscript.
  3. M. Hutton, J. Rose, D. Corneil, "Generation of Synthetic Sequential Benchmark Circuits," in FPGA `97, ACM Symp. on FPGAs, Feb 1997, pp. 149-155. Postscript.
  4. S. Wilton, J. Rose, Z. Vranesic, "Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays," in FPGA `97, ACM Symp. on FPGAs, Feb 1997, pp. 10-16. Postscript.
  5. D. Lewis, D. Galloway, M. van Ierssel, J. Rose, P. Chow, "The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System," in FPGA `97, ACM Symp. on FPGAs, Feb 1997, pp. 53-61. Postscript.
  6. V. Betz and J. Rose, "Directional Bias and Non-Uniformity in FPGA Global Routing Architectures," in ICCAD 1996, pp. 652-659, November 1996. FPGA '95, pp. 10-16. Postscript
  7. M. Hutton, J.P. Grossman, J. Rose, D. Corneil, "Characterization and Parameterized Random Generation of Digital Circuits," in the 1996 Design Automation Conference, June, 1996, pp. 94-99. Postscript.
  8. S. Wilton, J. Rose, Z. Vranesic, " Memory/Logic Interconnect Flexibility in FPGAs with Large Embedded Memory Arrays ," in CICC 96, the IEEE Custom Integrated Circuits Conf., San Deigo, CA, May 1996, pp. 144-147. Postscript
  9. T. Ngai, J. Rose, S. Wilton, " An SRAM-Programmable Field-Configurable Memory ," in CICC 95, the IEEE Custom Integrated Circuits Conf., Santa Clara, CA, May 1995, pp. 499-502. Postscript
  10. V. Betz, J. Rose, "Improving FPGA Performance via the Use of Architecture Families," 3rd ACM Intl Symposium on Field-Programmable Gate Arrays, FPGA '95, pp. 10-16. Postscript
  11. S. Wilton, J. Rose, Z. Vranesic, " Architecture of Centralized Field-Configurable Memory ," 3rd ACM Intl Symposium on Field-Programmable Gate Arrays, FPGA 95, pp. 97-103. Postscript
  12. D. Karchmer, J. Rose, "Definition and Solution of The Memory Packing Problem for Field-Programmable Systems," in the ACM/IEEE International Conference on Computer-Aided Design, ICCAD 94, pp. 20-26.
  13. J. He, J. Rose, "Advantages of Heterogeneous Logic Block Architectures for FPGAs," IEEE Custom Integrated Circuits Conf. 1993, (CICC 93), San Diego, May 1993 pp. 7.4.1 - 7.4.5.
  14. P. Chow, S. Seo, K. Chung, G. Paez, J. Rose, "A High-Speed FPGA Using Programmable Mini-Tiles," in Symposium on Integrated Systems (formerly Conference on Advanced Research in VLSI), Washington, 1993, pp. 104-122.
  15. B. Fallah, J. Rose, "Timing-Driven Routing Segment Assignment in FPGAs," in the Canadian Conference on VLSI, CCVLSI 92, October 1992, pp. 124-130.
  16. B. Tseng, J. Rose, S. Brown, "Using Architectural and CAD Interactions to Improve FPGA Routing Architectures," in the IEEE, ICCD 92 October 1992, pp. 99 - 104.
  17. K. Chung, J. Rose, "TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections," Proc. 29th ACM/IEEE Design Automation Conference, June 1992, Anaheim, CA, pp. 361-367.
  18. R.J Francis, J. Rose, Z. Vranesic, "Technology Mapping Lookup Table-Based FPGAs for Performance" Proc. 1991 IEEE International Conference on Computer-Aided Design (ICCAD), November 1991, pp. 568-571.
  19. R.J Francis, J. Rose, Z. Vranesic, "Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs," 28th ACM/IEEE Design Automation Conference, June 1991, pp. 227-233.
  20. S. Singh, J. Rose, D. Lewis, K. Chung, P. Chow "Optimization of Field-Programmable Gate Array Logic Block Architecture for Speed," in IEEE Custom Integrated Circuits Conference 91, CICC, May 1990, pp. 6.1.1 - 6.1.6.
  21. S. Brown, J.S. Rose, Z. Vranesic, "A Detailed Router for Field Programmable Gate Arrays" Proc. 1990 IEEE International Conference on Computer-Aided Design (ICCAD), pp. 382-385, November 1990. Designated as a distinguished paper.
  22. R.J Francis, J. Rose, K. Chung, "Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays," Proc. 27th ACM/IEEE Design Automation Conference, June 1990, pp. 613-619.
  23. J. Rose, S. Brown, "The Effect of Switch Box Flexibility on Routability of Field Programmable Gate Arrays," IEEE Proc. Custom Integrated Circuits Conference, (CICC), Boston May 1990, pp. 27.5.1 - 27.5.4.
  24. J.S. Rose, R.J. Francis, P. Chow, and D. Lewis, "The Effect of Logic Block Complexity on Area of Programmable Gate Arrays," Proc. IEEE Custom Integrated Circuits Conference, (CICC), San Diego, May 1989, pp. 5.3.1 - 5.3.5.
  25. J.S. Rose, W. Klebsch, J. Wolf, "Temperature Measurement of Simulated Annealing Placements," in IEEE International Conference on Computer-Aided Design, (ICCAD), November 1988, pp. 514-517.
  26. J.S. Rose, "The Parallel Decomposition and Implementation of an Integrated Circuit Global Router," ACM Sigplan Symposium on Parallel Programming: Experience with Applications, Languages and Systems, July 1988, pp. 138-145.
  27. J.S. Rose, "LocusRoute: A Parallel Global Router for Standard Cells," Proc. 25th Design Automation Conference, June 1988, pp. 189-195.
  28. J.S. Rose, D.R. Blythe, W. Snelgrove, Z. Vranesic, "Fast, High Quality VLSI Placement on an MIMD Multiprocessor," Proc. ICCAD 86, Nov. 1986, pp. 42-45.
  29. Z.G. Vranesic, J.S. Rose, W.M. Loucks, "A Flexible Architecture MIMD Supercomputer for Non-Numeric Applications," First International Conference on Supercomputing Systems, December 1985, pp. 455-459.
  30. J.S. Rose, W.M. Snelgrove, Z.G. Vranesic, "ALTOR: An Automatic Standard Cell Layout Program," 1985 Canadian Conference on Very Large Scale Integration, November 1985, pp. 169-173. This paper won a best paper award.

Refereed Presentations at Workshops

  1. M. Khalid and J. Rose, "Experimental Evaluation of Mesh and Partial Crossbar Routing Architectures for Multi-FPGA Systems" to appear at the International Workshop on Logic Architecture and Synthesis, Grenoble, December 1997. Postscript
  2. V. Betz and J. Rose, "VPR: A New Packing, Placement and Routing Tool for FPGA Research," to appear at London Workshop on Field-Programmable Logic, August 1997. Postscript
  3. M. Khalid and J. Rose, "The Effect of Fixed I/O Pin Positioning on The Routability and Speed of FPGAs," Proc. Canadian Workshop of Field-Programmable Devices, FPD 95, pp. 94-102.
  4. D. Galloway, D. Karchmer, P. Chow, D. Lewis, J. Rose, "The Transmogrifier: The University of Toronto Field-Programmable System," in the 1994 Canadian Workshop on Field-Programmable Devices. (formerly the CMC VLSI Workshop) Postscript
  5. J. He, J. Rose, "Technology Mapping for Heterogeneous FPGAs," in the ACM International Workshop on Field-Programmable Gate Arrays 1994, February 1994, FPGA '94. Postscript
  6. K. Chung, S. Singh, J. Rose, P. Chow, "Using Hierarchical Logic Blocks to Improve the Speed of Field-Programmable Gate Arrays," International Workshop on Field Programmable Logic and Applications, Sept 1991, Oxford, UK.
  7. P. Chow, S.O. Seo, D. Au, B. Fallah, C. Li, J.Rose, "A 1.2um CMOS FPGA Using Cascaded Logic Blocks and Segmented Routing," International Workshop on Field Programmable Logic and Applications, Sept 1991, Oxford, UK.
  8. J-M. Vuillamy, Z. Vranesic, J.Rose, "Performance Evaluation and Enhancement of FPGAs," International Workshop on Field Programmable Logic and Applications, Sept 1991, Oxford, UK.

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