last day: DRAM

___
RAS:
_______                                      ______
       \____________________________________/
                                           on
                                           a
                                           read,  
                                           this
                                           is
                                           where
                                           data
                                           latched
                                           in


___
CAS:
____________________                   ____________
                    \_________________/
                                      on
                                      a
                                      write,
                                      this
                                      is
                                      where
                                      data
                                      latched
                                      in 


___
RAS:
_______                                      ______
       \____________________________________/
                                           on
                                           a
                                           read,  
                                           this
                                           is
                                           where
                                           data
                                           latched
                                           in


burst transfer to cache: column access time typ. 7nsec (as compared to, say, 90nsec row access time)

___
RAS:                   90nsec
_______                                      ______
       \____________________________________/
                                           on
                                           a
                                           read,  
                                           this
                                           is
                                           where
                                           data
                                           latched
                                           in

___
CAS:     7nsec
_________      _____      ____      ___
         \____/     \____/    \____/



____
DATA:
            __________  _________  ________
___________/          \/         \/
           \__________/\_________/\________


(and explanation of transistor memory cells,
digression to how a transistor works...
digression to how its predecessor works...
(5U4, 5Z4), etc., efficiency of filaments made close to plates...

examples to pass around class...

SRAM

theory of operation of SRAM


going further

IEEE Trans. Multimedia june 1999, page 121, analog RAM chip video conferencing cameras for mpeg4, for optical flow. 16 by 256 analog memory chip. 7 bits dynamic range, runs at 5MHz best for high bandwidth repetitive tasks small images e.g. (50 by 50 pixels). multiplexing in areas of pixels they calculate the transforms on, invariant codings, fourier transform, edge detection.

further opportunities for those interested in "stuff that matters"


announcement: if you like this course, you'd likely enjoy a summer job working in the personal cybernetics lab. if joining our personal cybernetics team is of interest, please contact me right after any of the lectures.

i also have a number of 4th year computer science thesis (cs495, cs494) projects available that could serve as a continuation of the "stuff that matters" learned in the course.

also projects next term (spring term).

summer and spring term projects avail:


EDO (extended data output) RAM

whatis.com/nfindex.htm
Extended data output (EDO) RAM is a type of random access memory (RAM) chip that improves the time to read from memory on faster microprocessors such as the Intel Pentium. EDO RAM was initially optimized for the 66 MHz Pentium. For faster computers, different types of synchronous dynamic RAM (SDRAM) are recommended. Also see BEDO DRAM.

SDRAM (synchronous dynamic random access memory)

whatis.com
Synchronous DRAM (SDRAM) is a generic name for various kinds of DRAM that are synchronized with the clock speed that the microprocessor is optimized for. This tends to increase the number of instructions that the processor can perform in a given time. The speed of SDRAM is rated in MHz rather than in nanoseconds (ns). This makes it easier to compare the bus speed and the RAM chip speed. You can convert the RAM clock speed to nanoseconds by dividing the chip speed into 1 billion ns (which is one second). For example, an 83 MHz RAM would be equivalent to 12 ns.