http://www.elec.uq.edu.au/~3e211/pracs/prac2/prac2.htm Dept. of Computer Science and Electrical Engineering The University of Queensland
flip-flops have 2 outputs:
A flip-flop circuit can be constructed from two NOR gates:
Each has two outputs, Q and Q', and two inputs, set and reset. This type of flip-flop is referred to as an SR flip-flop or SR latch.
two useful states:
In normal operation must avoid putting 1 on both inputs simultaneously.
or two NAND gates:
operates with inputs normally at 1 unless the state of the flip-flop has to be changed.
0 applied momentarily to the set input causes Q to go to 1 putting the flip-flop in the set state.
In normal operation must avoid putting 0 on both inputs simultaneously.
JK flip-flop is refinement of SR flip-flop in that the indeterminate state of the SR type is defined in the JK type.
Inputs J and K behave like inputs S and R to set and clear the flip-flop
the letter J is for set and the letter K is for clear
When logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its complement state, ie., if Q=1, it switches to Q=0 and vice versa.
A clocked JK flip-flop:
Output Q is ANDed with K and CP inputs so that the flip-flop is cleared during a clock pulse only if Q was previously 1.
Similarly, ouput Q' is ANDed with J and CP inputs so that the flip-flop is set with a clock pulse only if Q' was previously 1.
because of the feedback connection in the JK flip-flop, a CP signal which remains a 1 (while J=K=1) after the outputs have been complemented once will cause repeated and continuous transitions of the outputs. To avoid this, the clock pulses must have a time duration less than the propagation delay through the flip-flop. The restriction on the pulse width can be eliminated with a master-slave or edge-triggered construction.
T type flip-flop is single input version of JK flip-flop (both inputs connected together).
A master-slave flip-flop is constructed from two seperate flip-flops:
master flip-flop enabled on positive edge of clock pulse CP and slave flip-flop disabled by inverter.
When pulse returns to 0, master flip-flop disabled and slave flip-flop enabled.
slave flip-flop then goes to the same state as the master flip-flop.
The output state of the master-slave flip-flop occurs on the negative transition of the clock pulse.
Some master-slave flip-flops change output state on the positive transition of the clock pulse by having an additional inverter between the CP terminal and the input of the master.