DRAM read

row address selects a row.
when you drop (assert) RAS, row address gets latched

reason for reading and latching the entire row (refresh).

sense amplifier and comparator merely checks to see whether or not there was once a voltage present since the time a 1 was written. typically compares with 1/10, or so, of the max. voltage.

above is a 4 by 4 (16 bit) DRAM.

in actual practice, DRAM is larger, e.g. 128 by 128, with 7 bit row addr and 7 bit col. addr, giving 16384 bits (16K)

some are 128cols by 256 rows

modern DRAM may be 1024 by 1024 (1Mbit).

one chip for each bit, and sometimes parity or ECC.
(e.g. in DEC alpha, it must be ECC)

sometimes put 4 copies of same DRAM device on same die, e.g. 4Mbit DRAM, (easier than redesign to make a larger device... incrementalist approach).
called "nibble mode"

DRAM write