number of machine cycles per instruction = pipeline depth
typically pipeline depth is 5
other problems:
solution: introduce NOPs into the pipeline
examples of NOPs:
using these NOPs, the above may be rewritten:
what are some of the problems with this implementation of NOP?
structural hazards?
use of A and B, etc...
note that on many microprocessors, R0 is always 0, therefore can be used
without structural hazard, e.g. AND R0 R0 R0.
a better solution: do some useful instruction instead of a NOP:
continuing onward (store register C):
